1. Field of the Invention
The present invention relates to microprocessor testability, and in particular to providing full access to on-chip instruction cache and microcode ROM.
2. Description of the Related Art
The on-chip instruction cache of a microprocessor or microcontroller plays an important role in guaranteeing a high instruction throughput. It is therefore critical that the instruction cache operate properly. To do so requires that the instruction cache be tested for memory faults, such as stuck-at faults and cross coupling faults, among others. Testing is performed by writing a test pattern into the cache memory, and then reading out the data just written to verify the write operation. Alternatively, a test instruction can be written into the instruction cache and the execution stream observed to determine whether the instruction was correctly stored in the cache. The testability of caches has become increasingly important because as cache memory capacity and density have increased, the probability of less common defects occurring has increased.
The i960.RTM. CA/CF microprocessor, manufactured by the assignee of the present invention, achieves instruction cache verification through user-input instructions by storing dummy instructions in external memory, invalidating the entire instruction cache, and then posting a dummy instruction fetch so that the instruction cache is forced to retrieve and cache a dummy instruction from external memory. In a similar manner, a built-in self-test (BIST) routine that is incorporated into i960.RTM. CA/CF microcode can write dummy instructions into the instruction cache from internal on-chip registers, rather than external memory, by posting dummy instruction fetches. In either case, however, test patterns can only be written into the instruction data area of the instruction cache, and not into the tag array, the LRU (least recently used) bits, the tag valid bits or the word valid bits.
Access to those other areas of the cache could be achieved by providing extra registers into which are written the tags, the dummy instructions, and the associated valid and LRU bits. An extra on-chip state machine would then address the cache at a selected line and load the data from the extra registers into the cache tag and instruction arrays, and into the valid bits and the LRU bits. This scheme, however, would require extra on-chip hardware that would occupy an unacceptable amount of chip area and incur an excessive validation cost
For reasons similar to those given above, in the past it has been difficult to provide full access to microcode ROM memory cells without requiring extra on-chip hardware to provide full access, e.g., extra registers to hold the contents read from ROM and hardware to access those registers.
It is thus desired to provide an efficient means to access all parts of an on-chip instruction cache and microcode ROM while occupying only a small amount of additional chip area.